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a s3 4 2 1 a s 3 4 22 l o w p o w e r a m b i e n t no i s e- c an ce l l i n g s p e a k er dr i ve r www.austriamicrosystems.com revision 0.90 1 61 d a tas hee t 1 general description the as3421/22 are speaker driver with ambient noise cancelling function for headsets, headphones or ear pieces. it is intended to improve quality of e.g. music listening, a phone co nversation etc. by reducing background ambient noise. the fully analog implementation allows the lowest p ower consumption, lowest system bom cost and most natura l received voice enhancement otherwise difficult to achieve wi th dsp implementations. the device is designed to be easil y applied to existing architectures. an internal otprom can be optionally used to store the microphone gain calibration settings as well as all application specific settings. the as3421/22 can be used in different configuratio ns for best tradeoff of noise cancellation, required filtering functions and mechanical designs. the simpler feedforward topology is used to effect ively reduce frequencies typically up to 23khz. the feedback t opology with either 1 or 2 filtering stages has it strengths esp ecially at very low frequencies. the typical bandwidth for feedback sys tem is from 20hz up to 1khz which is a little bit lower than with fe ed forward systems. the filter loop for both systems is determined by m easurements, for each specific headset individually, and depends ver y much on mechanical designs. the gain and phase compensation filter network is implemented with cheap resistors and cap acitors for lowest system costs. as3421/22 features also an audio playback only mode which allows the user to easily switch between anc on and off mo de. in anc off mode unused blocks are automatically switch off to guaranty lowest power consumption in each operating mode. 2 key features microphone input 128 gain steps @ 0.375db and mute with agc differential, low noise microphone amplifier single ended or differential mode improved supply for electret microphone mic gain otp programmable high efficiency headphone amplifier 2x23mw, 0.1% thd+n @ 32 w , 1.5v supply, 100db snr bridged mode for e.g. 300 w loads click and pop less startup and mode switching line input volume control via serial interface or push buttons 64 steps @ 0.75db and mute, popfree gain setting fully differential stereo line inputs anc processing feedforward cancellation feedback cancellation with filter loop transfer fu nction definable via simple rc components simple in production sw calibration 1230db noise reduction (headset dependent) 103000hz wide frequency active noise attenuation ( headset dependent) monitor function for assisted hearing, i.e. to monitor announcements fixed (otp prog.) ambient sound amplification to co mpensate headphone passive attenuation incremental functions anc with or without music on the receiving path music playback mode for lowest power consumption otp rom for automatic trimming during production (4 times programmable) performance parameter 7ma @ 1.5v stereo anc; <1a quiescent extended psrr for 217hz increased tdma noise immunity interfaces 2wire serial control mode & volume inputs calibration via linein or 2wire serial interface fixed 1.01.8v supply with internal cp package as3421 qfn24 [4x4mm] 0.5mm pitch as3422 qfn32 [5x5mm] 0.5mm pitch 3 applications the devices are ideal for wireless devices like ste reo bluetooth headsets as well as stereo wireless headsets.
www.austriamicrosystems.com revision 0.90 2 61 as3421 as3422 datasheet a p p l i c a t i o n s figure 1. as3421 feed forward anc block diagram figure 2. as3422 feed-back block diagram
www.austriamicrosystems.com revision 0.90 3 61 as3421 as3422 datasheet c o n t e n t s 4 contents 1 general description ............................. ................................................... ................................................... ............................... 1 2 key features.................................... ................................................... ................................................... ................................... 1 3 applications.................................... ................................................... ................................................... ..................................... 1 4 contents........................................ ................................................... ................................................... ...................................... 3 5 pin assignments ................................. ................................................... ................................................... ................................ 4 5.1 pin descriptions.............................. ................................................... ................................................... ................................................ 5 6 absolute maximum ratings ........................ ................................................... ................................................... ........................ 6 7 electrical characteristics...................... ................................................... ................................................... ............................... 7 8 typical operating characteristics ............... ................................................... ................................................... ........................ 8 9 detailed description ................................................... ................................................... ................................................... .......11 9.1 audio line input ................................................... ................................................... ................................................... ........................ 11 9.2 microphone input ................................................... ................................................... ................................................... ...................... 12 9.3 headphone output ................................................... ................................................... ................................................... .................... 14 9.4 operational amplifier ................................................... ................................................... ................................................... ................. 15 9.5 system ................................................... ................................................... ................................................... ................................... 17 9.6 vneg charge pump ................................................... ................................................... ................................................... ................. 20 9.7 otp memory & internal registers ................................................... ................................................... ............................................... 20 9.8 2wireserial control interface ................................................... ................................................... ................................................... .. 23 10 register description ................................................... ................................................... ................................................... .... 27 11 application information ................................................... ................................................... ................................................... 43 11.1 as3422 feedback application examples ................................................... ................................................... .................................. 43 11.2 as3421 feed forward application examples ................................................... ................................................... ............................ 47 11.3 layout recommendation ................................................... ................................................... ................................................... ....... 51 11.4 bill of materials ................................................... ................................................... ................................................... ....................... 52 11.5 pcb footprint recommendation ................................................... ................................................... ................................................ 53 12 package drawings and marking ................... ................................................... ................................................... ..... ................. 55 ordering information ............................... ................................................... ................................................... ............................... 59
www.austriamicrosystems.com revision 0.90 4 61 as3421 as3422 datasheet p i n a s s i g n m e n t s 5 pin assignments note: pin assignment may change in preliminary data sheet s. figure 3. pin assignments (top view) caution: exposed pad must be connect to vneg or left unconn ected. exposed pad must not be connected to gnd or agnd!
www.austriamicrosystems.com revision 0.90 5 61 as3421 as3422 datasheet p i n a s s i g n m e n t s 5.1 pin descriptions note: pin description may change in preliminary data shee ts. table 1. pin description for as3421 as3422 pin name pin number type description as3421 as3422 iop1l 24 1 ana in filter opamp1 input left channel qlinl 2 ana out line in gain stage output left channel qmicl 1 3 ana out mic gains tage output right channel agnd 2 4 ana in analog reference linl_n 3 5 ana in negative line in pin of left channel linl_p 4 6 ana in positive line in pin of left channel linr_p 5 7 ana in positive line in pin of right channel linr_n 6 8 ana in negative line in pin of right channel anc_csda 7 9 mixed io serial interface data anc pin (enable/disable anc function) mode_cscl 8 10 dig in mode pin (power up/down, monitor) serial interface clock micl 9 11 ana in microphone in left channel mics 10 12 ana out microphone supply micr 11 13 ana in microphone input right channel qmicr 12 14 ana out mic gain stage output right channel qlinr 15 ana out line in gain stage output right channel iop1r 13 16 ana in filteropamp1 input right channel qop1r 14 17 ana in filter opamp1 output right channel iop2r 18 ana in filter opamp2 input right channel qop2r 19 ana out filter opamp2 output right channel vss 20 sup in vss supply terminal hpl 15 21 ana out headphone output left channel hpvss 22 sup in headphone amplifier vss supply terminal hpr 16 23 ana out headphone output right channel hpvdd 17 24 sup in headphone vdd supply vbat 18 25 sup in positive supply terminal of ic cpp 19 26 ana out vneg chargepump flying capacitor positive terminal gnd 20 27 gnd vneg chargepump negative supply cpn 21 28 ana out vneg chargepump flying capacitor negative terminal vneg 22 29 sup io vneg chargepump output qop2l 30 ana out filter opamp2 output left channel iop2l 31 ana in filter opamp2 input left channel qop1l 23 32 ana out filter opamp1 output right channel vneg 25 33 sup in exposed pad: connect to vneg or leave it unconnecte d
www.austriamicrosystems.com revision 0.90 6 61 as3421 as3422 datasheet a b s o l u t e m a x i m u m r a t i n g s 6 absolute maximum ratings stresses beyond those listed in table 2 may cause permanent damage to the device. these ar e stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in electrical characteristics on page 7 is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. the device should be ope rated under recommended operating conditions. table 2. absolute maximum ratings parameter min max units comments reference ground defined as in gnd supply terminals 0.5 2.0 v applicable for pin vbat, hpvdd ground terminals 0.5 0.5 v applicable for pins agnd negative terminals 2.0 0.5 v applicable for pins vneg, vss, hpvss voltage difference at vss terminals 0.5 0.5 v applicable for pins vss, hpvss pins with protection to vbat vneg 0.5 5.0 vbat+0.5 v applicable for pins cpp, cpn pins with protection to hpvdd vss 0.5 5.0 hpvdd+0.5 v applicable for pins linl_p/n, linr_p/n, micl/ r, hpr, hpl, qmicl/r, qlinl/r, iopx, qopx other pins vss 0.5 5 applicable for pins mics, anc_csda, mode_cscl input current (latchup immunity) 100 100 ma norm: jedec 17 continuous power dissipation (t a = +70oc) continuous power dissipation 200 mw p t 1 for qfn16/24/32 package 1. depending on actual pcb layout and pcb used electrostatic discharge electrostatic discharge hbm +/2 kv norm: jedec jesd22a114c temperature ranges and storage conditions junction temperature +110 oc storage temperature range 55 +125 oc humidity noncondensing 5 85 % moisture sensitive level 3 represents a max. floor life time of 168h package body temperature 260 oc the reflow peak soldering temperature (body temperature) specified is in accordance with ipc/ jedec j-std-020moisture/reflow sensitivity classification for non-hermetic solid state surface mount devices.
www.austriamicrosystems.com revision 0.90 7 61 as3421 as3422 datasheet e l e c t r i c a l c h a r a c t e r i s t i c s 7 electrical characteristics vbat = 1.0v to 1.8v, t a = 20oc to +85oc. typical values are at vbat = 1.5 v, t a = +25oc, unless otherwise specified. all limits ar e guaranteed. the parameters with min and max values are guarante ed with production tests or sqc (statistical qualit y control) methods. table 3. electrical characteristics symbol parameter condition min max unit t a ambient temperature range 20 +85 c supply voltages gnd reference ground 0 0 v vbat, hpvdd battery supply voltage normal operation with mode pin high 1.0 1.8 v two wire interface operation 1.4 1.8 v vneg chargepump voltage 1.8 0.7 v vss analog neg. supply voltages hpvss, vss, vneg 1.8 0.7 v v delta difference of ground supplies gnd, agnd to achieve good performance, the negative supply terminals should be connected to low impedance ground plane. 0.1 0.1 v v delta difference of negative supplies vss, vneg, hpvss charge pump output or external supply 0.1 0.1 v v delta + difference of positive supplies vbathpvdd 0.25 0.25 v other pins v mics microphone supply voltage mics 0 3.6 v v hpvdd pins with diode to hpvdd micl/r, hpr, hpl, qmicl/r, qlinl/r, iopx, qopx vss 3.6 v v vbat pins with diode to vbat cpp, cpn vneg vbat v v control control pins mode_cscl, anc_csda vss 3.7 v v trim line input & application trim pins linl_p, linl_n, linr_p, linr_n vneg 0.5 or 1.8 hpvdd +0.5 or 1.8 v symbol parameter condition min typ max unit i leak leakage current vbat<0.8v 20 a vbat<0.6v 10 a block power requirements @ 1.5v vbat i off off mode current mode pin low, device switched off 1 a i sys reference supply current bias generation, oscillator, adc6, vneg 0.25 ma i lin linein gain stage current no signal, stereo 0.5 ma i mic mic gain stage current no signal, stereo 2.10 ma i hp headphone stage current no signal 1.70 ma i mics mics charge pump current no load 30 a i min minimal supply current sum of all above blocks 4.6 ma i op1 op1 supply current no load 0.64 ma i op2 op2 supply current no load 0.64 ma
www.austriamicrosystems.com revision 0.90 8 61 as3421 as3422 datasheet e l e c t r i c a l c h a r a c t e r i s t i c s i micb microphone bias current 200a per microphone via charge pump 0.9 ma i pb low power playback mode v bat = 1.8v 2,8 ma v bat = 1.5v 2,5 ma v bat = 1.0v 2 ma symbol parameter condition min typ max unit
www.austriamicrosystems.com revision 0.90 9 61 as3421 as3422 datasheet ty p i c a l o p e r a t i n g c h a r a c t e r i s t i c s 8 typical operating characteristics v bat = +1.5v, c 1 =100nf, c 2 =10f, c 3 =1f, c 6 =100nf, c 5 =10f, c 13 =10f, c 12 =2.2f, c14=2.2f t a = +25oc and hp_mux_otp set to 3 unless otherwise specified. figure 4. thd+n vs. pout; line to hph; 16 w single ended stereo figure 5. thd+n vs. pout; l ine to hph; 32 w single ended stereo 0,01 0,1 1 10 1 10 100 thd+n [%] pout [mw] 1v 1.5v 1.8v 0,01 0,1 1 10 1 10 100 thd+n [%] pout [mw] 1v 1.5v 1.8v figure 6. thd+n vs. f; line to hph; 1mw load per c hannel figure 7. thd+n vs. f; line to hph; 10mw lo ad per channel 0,0 0,5 1,0 1,5 0,001 0,01 0,1 1 10 100 1k 10k pout [mw] thd+n [%] f [hz] 16 ohm 32 ohm pout 0 5 10 15 0,001 0,01 0,1 1 10 100 1k 10k pout [mw] thd+n [%] f [hz] 16 ohm 32 ohm pout figure 8. thd+n vs. f; 20mw and 30mw per channel f igure 9. frequency response 30mw@16 w ; line to hph 0 10 20 30 0,001 0,01 0,1 1 10 100 1k 10k pout [mw] thd+n [%] f [hz] thd+n 16 ohm thd+n 32 ohm pout 16 ohm pout 32 ohm -0,5 -0,4 -0,3 -0,2 -0,1 0 0,1 0,2 0,3 0,4 0,5 10 100 1k 10k frequency response [db] f [hz]
www.austriamicrosystems.com revision 0.90 10 61 as3421 as3422 datasheet ty p i c a l o p e r a t i n g c h a r a c t e r i s t i c s figure 10. frequency response 20mw@32 w ; line to hph figure 11. microphone supply fft -0,5 -0,4 -0,3 -0,2 -0,1 0 0,1 0,2 0,3 0,4 0,5 10 100 1k 10k frequency response [db] f [hz] -160 -140 -120 -100 -80 -60 -40 -20 0 10 100 1k 10k vrms [dbv] f [hz] figure 12. v neg cp voltage vs. cp load current with different v bat supply voltages figure 13. v neg efficiency vs.i vneg with different v bat supply voltages -2 -1,5 -1 -0,5 0 0 25 50 75 100 125 150 175 200 v neg [v] i vneg [ma] 1.8v 1.5v 1.0v -2 -1,5 -1 -0,5 0 0 25 50 75 100 125 150 175 200 v neg [v] i vneg [ma] 1.8v 1.5v 1.0v figure 14. v mic_out vs. i mic_out 0 0,5 1 1,5 2 2,5 3 3,5 4 0 200 400 600 800 v mic_out [v] i mic_out [a] vbat = 1.8v vbat = 1.5v
www.austriamicrosystems.com revision 0.90 11 61 as3421 as3422 datasheet ty p i c a l o p e r a t i n g c h a r a c t e r i s t i c s figure 15. typical performance data, feed forward configuration with an over the ear headset figure 16. typical performance data, feedback conf iguration with an on ear headset -30 -25 -20 -15 -10 -5 0 5 10 10 100 1000 10000 anc performance [db] f [hz] feed forward topology - over the ear headset -30 -25 -20 -15 -10 -5 0 5 10 10 100 1000 10000 anc performance [db] f [hz] feedback topology - on ear headset
www.austriamicrosystems.com revision 0.90 12 61 as3421 as3422 datasheet d e t a i l e d d e s c r i p t i o n 9 detailed description this section provides a detailed description of the device related components. 9.1 audio line input the chip features one line input. the blocks can wo rk in mono differential or in stereo single ended m ode. in addition to the 12.525k w input impedance, linein has a termination resistor of 10k w which is also effective during mute to charge eventually given input capacitors. 9.1.1 gain stage the line in gain stage is designed to have 63 gain steps of 0.75db with a max gain of 0db plus mute pe r default. by setting the bit line gain +3db in register 0x33 the gain range can be changed from 46.5db....0db to 43.5db ....+3db. in default, the gain will be ramped up from mute to 0db during startup. there is a possibility to make the playback volume user controlled by the vol pin with an adc converted vol voltage or up/dow n buttons. if the device is configured to control t he line input volume via pushbuttons the device ramps the gain from 46.5db to 0db if no button is pressed. if a user presses a button whil e ramping up the ramping mechanism will be stopped automatically. in monitor mode, the gain stage can be set to an fi xed default attenuation level for reducing the loud ness of the music. to avoid unwanted pop noise in this special mode the internal state machi ne support very smooth gain fading to avoid unwante d acoustic effects. figure 17. fully differential stereo line inputs 9.1.2 parameter vbat=1.5v, t a = 25oc, unless otherwise specified. table 4. line input parameter symbol parameter condition min typ max unit v lin input signal level 0.6* vbat vbat v peak r lin input impedance 0db gain (12.5k // 10k) 5.6 k 46.5db gain (25k // 10k) 7.2 k mute 10 k rlin input impedance tolerance 30 % c lin input capacitance 5 pf a lin programmable gain 46.5 +0 db gain steps discrete logarithmic gain steps 0.75 db gain step accuracy 0.5 db a linmute mute attenuation 100 db
www.austriamicrosystems.com revision 0.90 13 61 as3421 as3422 datasheet d e t a i l e d d e s c r i p t i o n 9.2 microphone input the afe offers two microphone inputs and one low no ise microphone voltage supply (microphone bias). th e inputs can be switched to single ended or differential mode. figure 18. microphone input 9.2.1 gain stage & limiter the mic gain stage has programmable gain within 11 .25db+36db in 128 steps of 0.375db. as softstart function is implemented for an automa tic gain ramping implemented with steps of 4ms to f ade in the audio at the end of the startup sequence. a limiter automatically attenuates high input signa ls. the agc has 127 steps with 0.375db with a dynam ic range of the full gain stage. in some design it is necessary to switch of the agc functio nality. this can be done in register 0x17 by settin g bit 1. in monitor mode, the gain stage can be set to an fi xed (normally higher) gain level or be controlled b y the vol pin. 9.2.2 microphone supply the mics charge pump is providing a proper micropho ne supply voltage for low supply voltage supply. th e integrated microphone supply supports basically 3 different modes. the first mode, also called switchmode, for 1.8v s upply is to have a direct connection with an integr ated switch from vbat to mics. the microphone supply pin of as3421/22 is in this mode directly connected to v bat . for some applications a 1.8v microphone supply is high enough to operate a microphone properly. this mode is more commonly used in devices with a fixed power supply like in bluetooth headsets. the internal microphone charge pump is switched off in this mode. this can help also reducing the exte rnal filter capacitors for the microphone supply. please mind that the sensitivity of your mi crophone can be reduced in this mode. alin gain ramp rate button mode, tinit=400ms 80 ms/step monitor mode 8 v attack limiter activation level hpl/r start of neg. clipping v peak v decay limiter release level hpl/r vneg +0.3 v peak t attack limiter attack time 4 s t decay limiter decay time 8 ms table 4. line input parameter (continued) symbol parameter condition min typ max unit agnd micl stereo mode micr qmicr qmicl mono differential mode agnd micl micr qmicr qmicl agnd
www.austriamicrosystems.com revision 0.90 14 61 as3421 as3422 datasheet d e t a i l e d d e s c r i p t i o n the second mode, with the name charegpump_mode, is the most commonly used mode which is per default en abled. in this mode the internal charge pump is enabled. the charge pump do ubles the supply voltage of as3421/22 with a high o utput impedance of the charge pump in order to make external passive filters more effe ctive. if doubling the supply voltage is not enough the microphone supply can be switched to a special regulated mode which increases the output v oltage but with a little bit higher output noise. t his setting can be found in register 0x35. the third mode is the off mode. this mode allows th e user to switch of the microphone supply if not ne eded (e.g. playback without anc) 9.2.3 parameter vbat=1.5v, t a = 25oc unless otherwise specified. table 5. microphone input parameter symbol parameter condition min typ max unit v micin 0 input signal level a mic = 24db 40 mv p v micin 1 a mic = 30db 20 mv p v micin 2 a mic = 36db 10 mv p r micin input impedance micp to agnd 7.5 k w micin input impedance tolerance 7 +33 % c micin input capacitance 5 pf a mic programmable gain 11.25 +36 db gain steps discrete logarithmic gain steps 0.375 db gain step precision 0.15 db amic gain ramp rate tinit=64ms 4 ms/step v attack limiter activation level v peak related to vbat or vneg 0.67 1 v decay limiter release level 0.4 1 a miclimit limiter gain overdrive 127 @ 0.375db 36 db t attack limiter attack time 5 s/step t decaydeb limiter decay debouncing time 64 ms t decay limiter decay time 4 ms/step v mics microphone output voltage no output load 2.7 v i mics microphone supply current no output load 30 a r out_cp cp output resistance 400a load 900 w i mic_min microphone output current recommended minimum microphone output current @ vbat = 1.5v 170 a recommended minimum microphone output current @ vbat = 1.8v 300 a i mic_max microphone output current recommended maximum microphone output current @vbat = 1.5v 500 a recommended maximum microphone output current @vbat = 1.8v 700 a
www.austriamicrosystems.com revision 0.90 15 61 as3421 as3422 datasheet d e t a i l e d d e s c r i p t i o n 9.3 headphone output the headphone output is a true ground output using vneg as negative supply, designed to provide the au dio signal with 2x12mw @ 16 w 64 w , which are typical values for headphones. it is also capable to operate in bridged mode for higher impe dance (e.g. 300 w) headphone. in this mode the left output is carrying the inverted signa l of the right output shown in figure 20 . figure 19. headphone output single ended mode figure 20. headphone output differential mode 9.3.1 input multiplexer the signal from the lineinput gain stage gets summ ed at the input of the headphone stage with the mic rophone gain stage output, the first filter opamp output or the second filter opamp output. the microphone gain stage output is used per default. it is also possible to playback without anc by only using the lineinput gain stage with no other signal on the multiplexer. for the monitor mode, the setting of this input mul tiplexer can be changed to another source, normally to the microphone. 9.3.2 no-pop function the nopop startup of the headphone stage takes 60m s to 120ms dependent on the supply voltage. 9.3.3 no-clip function the headphone output stage gets monitored by compar ator stages which detect if the output signal start s to clip. this signal is used to reduce the linein gain to av oid distortion of the output signal. a hystereses a voids jumping between 2 gain steps for a signal with constant amplitude. pop click control hpr hpl agnd lineinr mux qop2r qop1r qmicr lineinl mux qop2l qop1l qmicl hpvss hpvdd open open linein gain stage
www.austriamicrosystems.com revision 0.90 16 61 as3421 as3422 datasheet d e t a i l e d d e s c r i p t i o n 9.3.4 over-current protection the overcurrent protection has a threshold of 150 200ma and a debouncing time of 8s. the stage is fo rced to off mode in an overcurrent situation. after this, the headphone stage tries to power up again every 8ms as long as the overcurre nt situation still exists or the stage is turned off manually. 9.3.5 parameter vbat=1.5v, t a = 25oc, unless otherwise specified. 9.4 operational amplifier while as3421 offers only one operational amplifier for feedforward anc, as3422 features an additional operational amplifier stage to support feedback anc or any other additional needed filter ing. both operational amplifiers stages can be activated and used individually. while op1 stage is always c onfigured as inverting amplifier, op2 stage can be also switched to a noninverting mode with an adjustable gain of 0...+10.5db. figure 21. operational amplifiers table 6. headphone output parameter symbol parameter condition min typ max unit r l_hp load impedance stereo mode 16 w c l_hp load capacitance stereo mode 100 pf p hp nominal output power rl=64 w 12 mw rl=32 w 24 mw rl=16 w 34 mw p srrhp power supply rejection ratio 200hz20khz, 720mvpp, rl=16 90 db agnd iop1l op1 iop1r qop1r qop1l iop2l op2 non-inverting mode iop2r qop2r qop2l agnd 0..10.5db agnd 0..10.5db agnd iop2l op2 inverting mode iop2r qop2r qop2l
www.austriamicrosystems.com revision 0.90 17 61 as3421 as3422 datasheet d e t a i l e d d e s c r i p t i o n 9.4.1 parameter vbat=1.5v, t a = 25oc, unless otherwise specified. table 7. headphone output parameter symbol parameter condition min typ max unit r l_op load impedance single ended 1 k w c l_op load capacitance single ended 100 pf gbw op gain band width 4.3 mhz v os_op offset voltage 6 mv v ein_hp equivalent input noise 200hz20khz 2.6 v
www.austriamicrosystems.com revision 0.90 18 61 as3421 as3422 datasheet d e t a i l e d d e s c r i p t i o n 9.5 system the system block handles the power up and power dow n sequencing, as well as, the mode switching. 9.5.1 power up/down conditions the chip powers up when one of the following condit ions is true: the chip automatically shuts off if one of the foll owing conditions arises: 9.5.2 start-up sequence the startup sequence depends on the used mode. in standalone mode the sequence runs automatically , in i2c mode(i2c mode bit has to be pretrimmed) t he sequence runs till a defined state and waits then for an i2c command. either the autom atic sequence is started by setting the cont_pwrup bit in addition to the pwr_hold bit. if only the pwr_hold is set all enable bits for headphone, microphone, etc have to be set manually. figure 22. stand-alone mode start-up sequence table 8. power up conditions # source description 1 mode_cscl pin in standalone mode, mode pin has to be driven high to turn on the device 2 i2c start in i2c mode, a i2c start condition turns on the dev ice table 9. power down conditions # source description 1 mode pin power down by driving mode_cscl pin to low 2 serif power down by serif writing 0h to register 20h bit <0> 3 low battery power down if vbat is lower than the supervisor off threshold 4 vneg cp ovc power down if vneg is higher than the vneg offthre shold
www.austriamicrosystems.com revision 0.90 19 61 as3421 as3422 datasheet d e t a i l e d d e s c r i p t i o n figure 23. i2c mode start-up sequence the total startup time (including fadein of the g ain stages) can be reduced to 600ms by otp setting. 9.5.3 mode_cscl switching when the chip is in standalone mode (no i2c contro l), the mode can be switched with different levels on the mode pin. in i2c mode, the monitor mode can be activated be s etting the corresponding bit in the system register . table 10. mode_cscl operation modes mode mode_cscl pin description off low (vss) chip is turned off anc high (vbat) chip is turned on and active noise cancellation is active monitor vbat/2 chip is turned on and monitor mode is active in monitor mode, a different (normally higher) micr ophone preamplifier gain can be chosen to get an amplification of the surrounding noise. this vol ume can be either fixed or be controlled by the vol input. to get rid of the low pass filtering needed for the noise cancellation, the headphone input multiplexer can be set to a different (normally to mic) source. in addition, the linein gain can be lowered to redu ce the loudness of the music currently played back.
www.austriamicrosystems.com revision 0.90 20 61 as3421 as3422 datasheet d e t a i l e d d e s c r i p t i o n 9.5.4 anc_csda switching for bluetooth applications it is sometimes a requir ement to switch off the anc function while listenin g to music or having a phone call. because the fully differential audio outputs of the bluetoo th chip are directly connected to the line input of the as3421/22 it is not possible to simply switch off the anc chip to do music playback without anc.i n order to avoid an expensive bypass path with mech anical or electrical switches the as3421/22 features a special low power audio playba ck mode. in this mode the device enters a low power mode where the anc function is disabled and the blocks which are not necessary in this mode are automatically switched off to safe sy stem power. this audio playback mode can be entered by simply pulling the anc_scda pin t o low. figure 24. anc / csda switching an example how to implement this feature is shown i n figure 24 . in default operation (anc enabled) the anc_csda p in is pulled high. if the device should enter the low power playback mode the pin is pulled low with the switch s1. once the pin is pulled low the device enters after 200ms the playback mode. as long as the pin is low the device stays in the playback only mode. if the feature is for some reason not required it can also be disabled by setting the bit no_pb_mode_ otp in register 0x33. once this bit is set to 1 t he status of pin anc_csda has no influence on the device any more. besides the low power playback mode the anc_csda pi n supports also volume control via push buttons. in order to enable this feature the corresponding bit vol_button_mode_otp is register 0 x33 has to be set to 1. once this bit is set, the device can not support the low power playback mode via anc_csda pin any more. an example on how to connect the push buttons for volume cont rol is shown in figure 24 with the push buttons s2 and s3. table 11. anc_csda operation modes no_pb_mode_otp bit vol_button_mode_otp bit anc_csda pin description 0 0 high normal anc operation 0 0 high > low device enters low power playback mode 0 0 low > high device returns to normal anc operation 1 0 x normal anc operation. no influence on operation via anc_csda pin. x 1 high volume control mode via button volume up x 1 high imp. volume control mode via button no volume change x 1 low volume control mode via button volume down
www.austriamicrosystems.com revision 0.90 21 61 as3421 as3422 datasheet d e t a i l e d d e s c r i p t i o n 9.6 vneg charge pump the vneg charge pump uses one external 1uf capacito r to generate a negative supply voltage out of the battery input voltage to supply all audio related blocks. this allows a trueground hea dphone output with no more need of external dcdeco upling capacitors. 9.6.1 parameter vbat=1.5v, t a = 25oc, unless otherwise specified. 9.7 otp memory & internal registers the otp memory consists of otp register and the otp fuses.the otp register can be written as often as wanted but will lose the content on power off. the otp fuses are intended to store basi c chip configurations as well as the microphone gai n settings to optimize the anc performance and get rid of sensitivity variations o f different microphones. burning the fuses can only be done once and is a permanent change, which means the fuses keep the content even if the chip is powered down. this as3421/22 offers 4 regis ter set for storing the microphone gain making it possible to change the gain 3 times for r ecalibration or other purposes. when the chip is controlled by a microcontroller vi a i2c, the otp memory dont has to be used. the chi p configuration can be stored in the flash memory of the bluetooth or wireless chipset. 9.7.1 register & otp memory configuration figure 25 is showing the principal register interaction. figure 25. register access registers 0x8, 0x9, 0xa, 0xb, 0xc and 0x21 have onl y effect when the corresponding reg_on bit is set , otherwise the chip operates with the otp register settings which are loaded from the otp fuses at every startup. all registers settings can be changed several times , but will loose the content on power off. when usi ng the i2c mode, the chip configuration has to be loaded from the micro controller after every startup. in stand alone mode the otp fuses have to be programmed for a permanent change of the chip configuration. a single otp cell can be programmed only once. per default, the cell is 0; a programmed cell will co ntain a 1. while it is not possible to reset a programmed bit from 1 to 0, multiple otp writ es are possible, but only additional unprogrammed 0bits can be programmed to 1. independent of the otp programming, it is possible to overwrite the otp register temporarily with an o tp write command at any time. this setting will be cleared and overwritten with the ha rd programmed otp settings at each powerup sequenc e or by a load operation. table 12. headphone output parameter symbol parameter condition min typ max unit v in input voltage vbat 1.0 1.5 1.8 v v out output voltage vneg 0.7 1.5 1.8 v c ext external flying capacitor 1 f otp register 10h...16h; 30h...35h otp fuses burn load register 0x8,0x9,0xa 0xb, 0xc, 0x21 otp write otp read i2c if normal i2c write normal i2c read register 8h...21h otp path is default but can be switched by register setting
www.austriamicrosystems.com revision 0.90 22 61 as3421 as3422 datasheet d e t a i l e d d e s c r i p t i o n the otp memory can be accessed in the following way s: load operation. the load operation reads the otp fuses and loads th e contents into the otp register. a load operation is automatically executed after each poweronreset. write operation. the write operation allows a temporary modification of the otp register. it does not program the otp. this operation can be invoked multiple times and will remain set w hile the chip is supplied with power and while the otp register is not modified with another write or load operation. read operation. the read operation reads the contents of the otp re gister, for example to verify a write command or to read the otp memory after a load command. burn operation. the burn operation programs the contents of the otp register permanently into the otp fuses. dont use old or nearly empty batteries for burning the fuses. attention: if you once burn the otp_lock bit, no further prog ramming, e.g. setting additional 0 to 1, of the otp can be done. for production, the otp_lock bit must be set to avo id an unwanted change of the otp content during the lifetime of the product. 9.7.2 otp fuse burning as many wireless applications like bluetooth single chip solutions support programmable solutions as w ell as rom versions it is in rom versions necessary to store microphone gain compens ation data and the general anc configuration inside the anc chip because there is not other way to configure the anc chip during startup. in order to guaranty successful trimming of as3421 /22 it is necessary to provide a decent environment for the trimming process. in figure 26 a principal block diagram is shown for trimming th e as3421/22 properly in production. figure 26. block diagram for production environmen t the most important block is the external power supply. usual ly it is possible to trim the as3421/22 with a sing le supply voltage of min. 1.7v in laboratory environment but as soon as it comes to m ass production we highly recommend buffering also v neg supply of the chip. as highlighted in the block diagram it is mandatory to get a volta ge difference between v pos and v neg of min. 3.4v to guaranty proper trimming of the de vice. no current sink capability, therefore it is possibl e to buffer it external with a negative power suppl y. the v neg voltage applied to v neg pin must be lower than the voltage created with the charge pump . this means if the typical v neg output voltage is 1.5v you can easily apply exter nally 1.7v. the charge pump switches then automatically i nto skip mode. important for applying an external buffer and switc hing on the anc device is the timing in order to av oid latch up on the anc device. the timing diagram in figure 2 shows clearly that it is import ant that there is a certain delay between vbat and the mode /cscl pin necessary. this delay is mandatory in order to guaranty that the device star ts up properly. in case as350x is used the delay be tween vbat and mode/cscl is not necessary. the mode /cscl pin powers the anc device up and the whole sequence to power up the internal charge pump of as34x0 and as350x takes approximately 1ms. once vneg is settle d the external vneg buffer (e.g. power supply) can be enabled in order to support the charge pump especially during the trim process whic h can now be started.
www.austriamicrosystems.com revision 0.90 23 61 as3421 as3422 datasheet d e t a i l e d d e s c r i p t i o n figure 27. timing diagram for v neg buffering to guaranty a successful trimming process it is imp ortant to follow exactly the predefined trimming se quence shown in figure 28 . as a first step it is important to do a register dump of all otp regis ters. this register backup in your system memory is a backup of all register setting and is n ecessary for the verification after the trim process to make sure that all bits are trimmed correctly. once the register dump has been done it is important to check the otp_lock in register 0x35. this register indicates if the device is already trimmed or not. in case this bit is set to 1 there is no more trimming possible. the device has obviously already been trimmed before. in case the bit is 0 there is initial or further trimming of the device possible. you enter the trim mode and start the tri mming process. once the trimming is done the most i mportant step is comparing the values trimmed to the device with the original register du mp we did right before we started with the actual t rimming process. if the verification was successful we know that all bits have been trimmed correctly to as3501/as3502. what is important to me ntion is that the as3502 and as3501 have a couple of test bits inside which are per def ault set to 1. we do not recommend overwriting th ese bytes. furthermore it is important to know that it is not possible to change bits once they are trimmed. with as3501 and as3502 it is possible to trim the device again if the main_lock bit is not set to 1 . what is not possible is, is changing a bit from 1 back to zero. if an additional trimming is done it is only possible to change bits from 0 to 1. an example would be the following. a register contains a value of 0x41. if the main_lock bit is not set to 1 you can basically retrim the part but it doesnt work to change the value from 0x41 to 0x40. what is possible would be a change from 0x41 to 0x43. it is important that all necessa ry bits are trimmed exactly like in the block diagr am shown in figure 28 . the internal state machine needs the main_lock bit as well as the altx_lock bi ts to determine the right microphone register at st artup of the device. if the main_lock bit and the altx_lock bits are not set co rrectly the result can be malfunction of the device . for detailed implementation of the i2c trimming the re is also an application note available which desc ribes the whole process in more detail and includes also some code examples.
www.austriamicrosystems.com revision 0.90 24 61 as3421 as3422 datasheet d e t a i l e d d e s c r i p t i o n figure 28. otp burning process 9.8 2-wire-serial control interface there is an i2c slave block implemented to have acc ess to 64 byte of setting information. the i2c address is: adr_group8 audio processors 8eh_write 8fh_read 9.8.1 protocol table 13. 2-wire serial symbol definition symbol definition rw note s start condition after stop r 1 bit sr repeated start r 1 bit dw device address for write r 1000 1110b (8eh) dr device address for read r 1000 1111b (8fh) wa word address r 8 bit a acknowledge w 1 bit n no acknowledge r 1 bit reg_data register data/write r 8 bit data (n) register data/read w 8 bit enter application trimm mode anc pre burning measurements main_lock set? write, burn otp fuses 30-35h, 16-17h set main_lock and seq_lock n y y n verification ok? leave application trimm mode device trimming failed leave application trim mode anc post burning measurements device trimming succeeded y n verification ok? trimm verification alt1_lock set? mic trimm #2 write, burn otp fuses 10-11h set alt1_lock n y alt2_lock set? mic trimm #3 write, burn otp fuses 12-13h set alt2_lock n y alt3_lock set? mic trimm #4 write, burn otp fuses 14-15h set alt3_lock n y no further mic trimming possible leave application trimm mode
www.austriamicrosystems.com revision 0.90 25 61 as3421 as3422 datasheet d e t a i l e d d e s c r i p t i o n figure 29. byte write figure 30. page write byte write and page write formats are used to write data to the slave. the transmission begins with the start condition, w hich is generated by the master when the bus is in idle state (the bus is free). the device write address is followed by the word address. afte r the word address any number of data bytes can be sent to the slave. the word address is incremented internally, in order to write subsequen t data bytes on subsequent address locations. for reading data from the slave device, the master has to change the transfer direction. this can be d one either with a repeated start condition followed by the deviceread address, or simply with a new transmission start followed by the devicere ad address, when the bus is in idle state. the deviceread address is always followed b y the 1st register byte transmitted from the slave. in read mode any number of subsequent register bytes can be read from the slave. the word address is incremented internally. p stop condition r 1 bit wa++ increment word address internally r during acknowledge as3421 as3422 (=slave) receives data as3421 as3422 (=slave) transmits data table 13. 2-wire serial symbol definition symbol definition rw note s dw a wa a reg_data a p write register wa++ s dw a wa a reg_data 1 a p write register wa++ reg_data 2 a write register wa++ reg_data n a write register wa++ ...
www.austriamicrosystems.com revision 0.90 26 61 as3421 as3422 datasheet d e t a i l e d d e s c r i p t i o n figure 31. random read random read and sequential read are combined format s. the repeated start condition is used to change t he direction after the data transfer from the master. the word address transfer is initiated with a start condition issued by the master while the bus is id le. the start condition is followed by the devicewrite address and the word address. in order to change the data direction a repeated st art condition is issued on the 1st scl pulse after the acknowledge bit of the word address transfer. after the reception of the deviceread ad dress, the slave becomes the transmitter. in this s tate the slave transmits register data located by the previous received word address vector. the m aster responds to the data byte with a notacknowle dge, and issues a stop condition on the bus. figure 32. sequential read sequential read is the extended form of random read , as more than one registerdata bytes are transfer red subsequently. in difference to the random read, for a sequential read the transferred registerdata bytes are responded by an acknowledge from the master. the number of data bytes transferred in one sequence is unlimited (con sider the behavior of the wordaddress counter). to terminate the transmission the master has to send a notacknowledge following the last da ta byte and generate the stop condition subsequentl y. figure 33. current address read to keep the access time as small as possible, this format allows a read access without the word addres s transfer in advance to the data transfer. the bus is idle and the master issues a start condi tion followed by the deviceread address. analogous to random read, a single byte transfer is terminated with a notacknowledge after the 1st register byte. analogous to sequential rea d an unlimited number of data bytes can be transferred, where the data bytes has to be resp onded with an acknowledge from the master. for term ination of the transmission the master sends a notacknowledge following the last data byt e and a subsequent stop condition. s dw a wa a n a read register wa++ data sr dr p s dw a wa a n a read register wa++ data sr dr p reg_data 2 a read register wa++ reg_data n ... a read register wa++ s n a read register wa++ data dr p reg_data 2 a read register wa++ reg_data n ... a read register wa++
www.austriamicrosystems.com revision 0.90 27 61 as3421 as3422 datasheet d e t a i l e d d e s c r i p t i o n 9.8.2 parameter figure 34. 2-wire serial timing vbat >=1.4v 1 , t a =25oc, unless otherwise specified. table 14. 2-wire serial parameter symbol parameter condition min typ max unit v csl cscl, csda low input level (max 30%vbat) 0 0.42 v v csh cscl, csda high input level cscl, csda (min 70%vbat) 0.98 v hyst cscl, csda input hysteresis 200 450 800 mv v ol csda low output level at 3ma 0.4 v tsp spike insensitivity 50 100 ns t h clock high time max. 400khz clock speed 500 ns t l clock low time max. 400khz clock speed 500 ns t su csda has to change tsetup before rising edge of cscl 250 ns t hd no hold time needed for csda relative to rising edge of cscl 0 ns ts csda h hold time relative to csda edge for start/stop/rep_start 200 ns t pd csda prop delay relative to low going edge of cscl 50 ns 1. serial interface operates down to vbat = 1.0v but with 100khz clock speed and degraded parameters. 8 1-7 cscl csda 8 9 8 1-7 8 9 8 1-7 8 9 start condition address r/w ack data ack data ack stop condition ts t su t h t l t hd t pd
www.austriamicrosystems.com revision 0.90 28 61 as3421 as3422 datasheet r e g i s t e r d e s c r i p t i o n 10 register description table 15. i2c register overview addr name b7 b6 b5 b4 b3 b2 b1 b0 audio registers 0007h reserved 08h mic_l mic_mode 0: stereosingleend 1: monodiff micl_vol<6:0> gain from micl to qmicl or mixer = mute, 11.25db.. .+36db; 127 steps of 0.375db 09h mic_r mic_reg_on 0: use reg 30h & 31h 1: use reg 08h & 09h micr_vol<6:0> gain from micr to qmicr or mixer = mute, 11.25db.. .+36db; 127 steps of 0.375db 0ah line_in lin_reg_on 0: use reg 33h and vol pin 1: use reg 0ah lin_gain_+3db 0: 0db max. line gain 1: +3db max. line gain lin_vol<5:0> 0: mute; 0x01..0x3f: gain from linr/l to qlinr/l or mixer = 46.5db...+0db; 63 steps of 0.75db with lin_gain_+3 db bit set to 0 0x01..0x3f: gain from linr/l to qlinr/l or mixer = 43.5db...+3db; 63 steps of 0.75db with lin_gain_+3 db bit set to 1 0bh gp_op_l hp_mux<1:0> 0: mic; 1: op1; 2: op2; 3: open op2l<3:0> 0: op2l inverting mode; 0x1..0xf: op2l non inverting mode gain = 0...10.5db ; 15 steps of 0.75db op2l_on op1l_on 0ch gp_op_r op_reg_on 0: use reg 34h 1: use reg 0bh & 0ch hp_mode 0: stereosingleend 1: monodiff op2r<3:0> 0: op2r inverting mode; 0x1..0xf: op2r non inverting mode gain = 0...10.5db ; 15 steps of 0.75db op2r_on op1r_on 0dh0fh reserved 18h1fh reserved system register 20h system design_version<3:0> 1001 reg3f_on monitor_on cont_pwrup pwr_hold 21h pwr_set pwr_reg_on 0: use reg 0x35 1: use reg 0x21h hp_on mic_on lin_on mics_cp_on mics_on low_bat pwrup_ complete 22h2fh reserved
www.austriamicrosystems.com revision 0.90 29 61 as3421 as3422 datasheet r e g i s t e r d e s c r i p t i o n otp register 10h anc_l2 test_bit_5 micl_vol_otp2<6:0> gain from micl to qmicl or mixer = mute, 11.25db.. .+36db; 127 steps of 0.375db 11h anc_r2 alt1_lock micr_vol_otp2<6:0> gain from micr to qmicr or mixer = mute, 11.25db.. .+36db; 127 steps of 0.375db 12h anc_l3 test_bit_6 micl_vol_otp3<6:0> gain from micl to qmicl or mixer = mute, 11.25db.. .+36db; 127 steps of 0.375db 13h anc_r3 alt2_lock micr_vol_otp3<6:0> gain from micr to qmicr or mixer = mute, 11.25db.. .+36db; 127 steps of 0.375db 14h anc_l4 test_bit_7 micl_vol_otp4<6:0> gain from micl to qmicl or mixer = mute, 11.25db.. .+36db; 127 steps of 0.375db 15h anc_r4 alt3_lock micr_vol_otp4<6:0> gain from micr to qmicr or mixer = mute, 11.25db.. .+36db; 127 steps of 0.375db 16h mics_cntr lowbat + 100mv del_ anc_mux 17h pwrup seq_lock fast_start<4:0> 0: ~900ms; 0eh: ~600ms lin_agc_off mic_agc_off 30h anc_l test_bit_1 micl_vol_otp<6:0> gain from micl to qmicl or mixer = mute, 11.25db.. .+36db; 127 steps of 0.375db 31h anc_r test_bit_2 micr_vol_otp<6:0> gain from micr to qmicr or mixer =mute, 11.25db... +36db; 127 steps of 0.375db 32h mic_mon mon_mode 0: fixed volume 1: adj. volume mic_mon_otp<6:0> gain from micl/r to qmicl/r or mixer = mute, 5.625 db...+41.6db; 0.375db steps, if mon_mode is set to 0 gain from micl/r to qmicl/r or mixer = mute, 5.625 db...+41.6db; 0.375db steps, adjustable by vol pin if mon_mode is set to 1 33h audio_set no_pb_mode_otp 0: pb mode enabled 1: pb mode disabled vol_button_ mode_otp 0: volume mode disabled 1: volume mode enabled line_gain_+3db otp 0: 0db max. line gain 1: +3db max. line gain mic_mode_ otp 0: stereosingleend 1: monodiff hp_mode_ otp 0: stereosingleend 1: monodiff lin_mon_atten<2:0> 0: no attenuation; 1..6: lin_vol<6:0> shift by 6db...36db 7: mute 34h gp_op hp_mux_otp<1:0> 0: mic; 1: op1; 2: op2; 3: op2_otp<3:0> 0: op2 inverting mode; 0x1..0xf: op2 non inverting mode gain = 0...10.5db; 15 steps of 0.75db op2_on_otp op1_on_otp 35h otp_sys main_lock 0: write reg 30h.. 35h 1: lock reg 30h..35h test_bit_3 mon_hp_mux<1:0> 0: mic; 1: op1; 2: op2; 3: cp_mode 0: low noise, low voltage 1: high output voltage; mics_cp_off i2c_mode 3eh config_1 extburnclk 3fh config_2 tm34 burnsw tm_reg3435 tm_reg3033 otp_mode<1:0> 0: read; 1: load; 2: write; 3: burn table 15. i2c register overview addr name b7 b6 b5 b4 b3 b2 b1 b0
www.austriamicrosystems.com revision 0.90 30 61 as3421 as3422 datasheet r e g i s t e r d e s c r i p t i o n table 16. mic_l register name base default mic_l 2-wire serial 00h offset: 08h left microphone input register configures the gain for the left microphone input a nd defines the microphone operation mode. this register is reset at por. bit bit name default access bit description 7 mic_mode 0 r/w selects the microphone input mode 0: single ended stereo mode 1: mono differential mode 6:0 micl_vol<6:0> 000 0000 r/w volume settings for left microphone input, adjustable in 127 steps of 0.375db 00 0000: mute 00 0001: 11.25 db gain 00 0010: 10.875 db gain .. 11 1110: 35.625 db gain 11 1111: 36 db gain table 17. mic_r register name base default mic_r 2-wire serial 00h offset: 09h right microphone input register configures the gain for the right microphone input and enables register 08h & 09h. this register is re set at por. bit bit name default access bit description 7 mic_reg_on 0 r/w defines which registers are used for the microphone settings. 0: settings of register 30h and 31h are used 1: settings of register 08h and 09h are used 6:0 micr_vol<6:0> 000 0000 r/w volume settings for righ t microphone input, adjustable in 127 steps of 0.375db 00 0000: mute 00 0001: 11.25b gain 00 0010: 10.875 db gain .. 11 1110: 35.625 db gain 11 1111: 36 db gain
www.austriamicrosystems.com revision 0.90 31 61 as3421 as3422 datasheet r e g i s t e r d e s c r i p t i o n table 18. line_in register name base default line_in 2-wire serial 00h offset: 0ah line input register configures the attenuation for the line input, defi nes the line input operation mode and enables regis ter 0ah. this register is reset at por. bit bit name default access bit description 7 lin_reg_on 0 r/w defines which source is used for the line input settings. 0: settings of register 33h and vol pin are used 1: register 0ah is used 6 line_gain_+3db 0 r/w selects the line input operating gain range. if this bit is set the gain range of the line input amplifiers is shifted by +3db. 0: line input gain range from -46.5db...0db 1: line input gain range from 43.5db...+3db 5:0 lin_vol<5:0> 00 0000 r/w volume settings for line i nput, adjustable in 63 steps of 0.75db. the followi ng gain settings are valid if line_gain_+3db bit is se t to 0. 00 0000: mute 00 0001:46.5db gain 00 0010:45.75db gain .. 11 1110:0.75db gain 11 1111:.0 db gain volume settings for line input, adjustable in 63 st eps of 0.75db. the following gain settings are valid if line_gain_+3db bit is se t to 1. 00 0000: mute 00 0001:43.5db gain 00 0010:42.75db gain .. 11 1110:+2.25db gain 11 1111:+3 db gain table 19. gp_op_l register name base default gp_op_l 2-wire serial 00h offset: 0bh left general purpose operational amplifier register enables the left opamp stages, defines opamp 2 mode and gain and sets the hp input multiplexer. this register is reset at por. bit bit name default access bit description 7:6 hp_mux<1:0> 00 r/w multiplexes the analog audio sig nal to hp amp 00: mic: selects qmicl/r output 01: op1: selects qop1l/r outputs 10:op2: selects qop2l/r output 11: open: no signal mixed together with the line in put signal 5:2 op2l<3:0> 0000 r/w mode and volume settings for lef t op2, adjustable in 15 steps of 0.75db 0000: op2l in inverting mode 0001: 0 db gain, op2l in non inverting mode 0001: 0.75 db gain, non inverting .., 1110: 9.75db gain, non inverting 1111:.10.5 db gain, non inverting
www.austriamicrosystems.com revision 0.90 32 61 as3421 as3422 datasheet r e g i s t e r d e s c r i p t i o n 1 op2l_on 0 r/w enables left op 2 0: left op2 is switched off 1: left op2 is enabled 0 op1l_on 0 r/w enables left op 1 0: left op1 is switched off 1: left op1 is enabled table 20. gp_op_r register name base default gp_op_r 2-wire serial 00h offset: 0ch right general purpose operational amplifier registe r enables the right opamp stages, defines opamp 2 mod e and gain and sets the hp mode. this register is reset at por. bit bit name default access bit description 7 op_reg_on 0 r/w defines which register is used for th e opamp and hp settings. 0: settings of register 33h and 34h are used 1: register 0b and 0ch are used 6 hp_mode 0 r/w selects the line input mode 0: single ended stereo mode 1: mono differential mode 5:2 op2r<3:0> 0000 r/w mode and volume settings for rig ht op2, adjustable in 15 steps of 0.75db 0000: op2r in inverting mode 0001: 0 db gain, op2r in non inverting mode 0001: 0.75 db gain, non inverting .., 1110: 9.75db gain, non inverting 1111:.10.5 db gain, non inverting 1 op2r_on 0 r/w enables right op 2 0: right op2 is switched off 1: right op2 is enabled 0 op1r_on 0 r/w enables right op 1 0: right op1 is switched off 1: right op1 is enabled table 19. gp_op_l register name base default gp_op_l 2-wire serial 00h offset: 0bh left general purpose operational amplifier register enables the left opamp stages, defines opamp 2 mode and gain and sets the hp input multiplexer. this register is reset at por. bit bit name default access bit description
www.austriamicrosystems.com revision 0.90 33 61 as3421 as3422 datasheet r e g i s t e r d e s c r i p t i o n table 21. system register name base default system 2-wire serial 31h offset: 20h system register this register is reset at a por. bit bit name default access bit description 7:4 design_version<3:0> 1001 r afe number to identify t he design version 1001: for chip version 1v1 3 testreg_on 0 r/w 0: normal operation 1: enables writing to test register 3eh & 3fh to co nfigure the otp and set the access mode. 2 monitor_on 0 r/w enables the monitor mode 0: normal operation 1: monitor mode enabled 1 cont_pwrup 0 r/w continues the automatic powerup seq uence when using the i2c mode 0: chip stops the power-up sequence after the suppl ies are stable, switching on individual blocks has to be done via i 2c commands 1: automatic powerup sequence is continued 0 pwr_hold 1 r/w 0: power up hold is cleared and afe wi ll power down 1: is automatically set to on after power on table 22. pwr_set register name base default pwr_set 2-wire serial 0x11 1111b (stand alone mode) 0x00 0000b (i2c mode) offset: 21h power setting register please be aware that writing to this register will enable/disable the corresponding blocks, while reading gets the actual status. it is not pos sible to read back e.g iled settings. this register is reset at por. bit bit name default access bit description 7 pwr_reg_on 0 r/w defines which register is used for t he power settings. 0: all blocks stay on as defined in the start-up se quence 1: register 21h is used 6 low_bat x r vbat supervisor status 0: vbat is above brown out level 1: bvdd has reached brown out level 5 pwrup_complete x r powerup sequencer status 0: power-up sequence incomplete 1: powerup sequence completed 4 hp_on 0 w 0: switches hp stage off 1: switches hp stage on x r 0: hp stage not powered 1: normal operation 3 mic_on 0 w 0: switches microphone stage off 1: switches microphone stage on x r 0: microphone stage not powered 1: normal operation
www.austriamicrosystems.com revision 0.90 34 61 as3421 as3422 datasheet r e g i s t e r d e s c r i p t i o n 2 lin_on 0 w 0: switches line input stage off 1: switches line input stage on x r 0: line input stage not powered 1: normal operation 1 mics_cp_on 0 w 0: switches microphone supply charge pump off 1: switches microphone supply charge pump on x r 0: microphone supply charge pump not powered 1: normal operation 0 mics_on 0 w 0: switches microphone supply off 1: switches microphone supply on x r 0: microphone supply not enabled 1: normal operation table 22. pwr_set register name base default pwr_set 2-wire serial 0x11 1111b (stand alone mode) 0x00 0000b (i2c mode) offset: 21h power setting register please be aware that writing to this register will enable/disable the corresponding blocks, while reading gets the actual status. it is not pos sible to read back e.g iled settings. this register is reset at por. bit bit name default access bit description
www.austriamicrosystems.com revision 0.90 35 61 as3421 as3422 datasheet r e g i s t e r d e s c r i p t i o n table 23. anc_l2 register name base default anc_l2 2-wire serial 80h (otp) offset: 10h left otp microphone input register (2nd otp option) configures the gain for the left microphone input. this is a special register, writing needs to be ena bled by writing 10b to reg 3fh first. this register is rese t at por and gets loaded with the otp fuse contents . bit bit name default access bit description 7 test_bit_5 1 r for testing purpose only 6:0 micl_vol_otp2 <6:0> 000 0000 r/w volume settings for left microphone inpu t, adjustable in 127 steps of 0.375db 00 0000: mute 00 0001: 11.25db gain 00 0010: 10.875 db gain .. 11 1110: 35.625db gain 11 1111: 36 db gain table 24. anc_r2 register name base default anc_r2 2-wire serial 00h (otp) offset: 11h right otp microphone input register (2nd otp option ) configures the gain for the left microphone input. this is a special register, writing needs to be ena bled by writing 10b to reg 3fh first. this register is rese t at por and gets loaded with the otp fuse contents . bit bit name default access bit description 7 alt1_lock 0 r/w 0: additional bits can be fused inside register 10h & 11h 1: otp fusing for register 10h & 11h gets locked, n o more changes can be done. 6:0 micr_vol_otp2 <6:0> 000 0000 r/w volume settings for right microphone inp ut, adjustable in 127 steps of 0.375db 00 0000: mute 00 0001: 11.25db gain 00 0010: 10.875 db gain .. 11 1110: 35.625db gain 11 1111: 36 db gain
www.austriamicrosystems.com revision 0.90 36 61 as3421 as3422 datasheet r e g i s t e r d e s c r i p t i o n table 25. anc_l3 register name base default anc_l3 2-wire serial 80h (otp) offset: 12h left otp microphone input register (3rd otp option) configures the gain for the left microphone input. this is a special register, writing needs to be ena bled by writing 10b to reg 3fh first. this register is rese t at por and gets loaded with the otp fuse contents . bit bit name default access bit description 7 test_bit_6 1 r for testing purpose only 6:0 micl_vol_otp3 <6:0> 000 0000 r/w volume settings for left microphone inpu t, adjustable in 127 steps of 0.375db 00 0000: mute 00 0001: 11.25db gain 00 0010: 10.875 db gain .. 11 1110: 35.625db gain 11 1111: 36 db gain table 26. anc_r3 register name base default anc_r3 2-wire serial 00h (otp) offset: 13h right otp microphone input register (3rd otp option ) configures the gain for the left microphone input. this is a special register, writing needs to be ena bled by writing 10b to reg 3fh first. this register is rese t at por and gets loaded with the otp fuse contents . bit bit name default access bit description 7 alt2_lock 0 r/w 0: additional bits can be fused inside register 12h & 13h 1: otp fusing for register 12h & 13h gets locked, n o more changes can be done. 6:0 micr_vol_otp3 <6:0> 000 0000 r/w volume settings for right microphone inp ut, adjustable in 127 steps of 0.375db 00 0000: mute 00 0001: 11.25db gain 00 0010: 10.875 db gain .. 11 1110: 35.625db gain 11 1111: 36 db gain
www.austriamicrosystems.com revision 0.90 37 61 as3421 as3422 datasheet r e g i s t e r d e s c r i p t i o n table 27. anc_l4 register name base default anc_l4 2-wire serial 80h (otp) offset: 14h left otp microphone input register (4th otp option) configures the gain for the left microphone input. this is a special register, writing needs to be ena bled by writing 10b to reg 3fh first. this register is rese t at por and gets loaded with the otp fuse contents . bit bit name default access bit description 7 test_bit_7 1 r for testing purpose only 6:0 micl_vol_otp4 <6:0> 000 0000 r/w volume settings for left microphone inpu t, adjustable in 127 steps of 0.375db 00 0000: mute 00 0001: 11.25db gain 00 0010: 10.875 db gain .. 11 1110: 35.625db gain 11 1111: 36 db gain table 28. anc_r4 register name base default anc_r4 2-wire serial 00h (otp) offset: 15h right otp microphone input register (4th otp option ) configures the gain for the left microphone input. this is a special register, writing needs to be ena bled by writing 10b to reg 3fh first. this register is rese t at por and gets loaded with the otp fuse contents . bit bit name default access bit description 7 alt3_lock 0 r/w 0: additional bits can be fused inside register 14h & 15h 1: otp fusing for register 14h & 15h gets locked, n o more changes can be done. 6:0 micr_vol_otp4 <6:0> 000 0000 r/w volume settings for right microphone inp ut, adjustable in 127 steps of 0.375db 00 0000: mute 00 0001: 11.25db gain 00 0010: 10.875 db gain .. 11 1110: 35.625db gain 11 1111: 36 db gain
www.austriamicrosystems.com revision 0.90 38 61 as3421 as3422 datasheet r e g i s t e r d e s c r i p t i o n table 29. mics_cntr register name base default mics_cntr 2-wire serial 00h (otp) offset: 16h microphone supply regsiter configures the low battery threshold value bit bit name default access bit description 3 lowbat 0 r/w 0: default lowbat value 1: 100mv increase of lowbat threshold 0 del_ anc_mux 0 r/w 0: default startup timing of as3421/22 1: hp_mux_otp is set to otp value 0.8s after device startup table 30. pwrup_cntr register name base default pwrup_cntr 2-wire serial 00h (otp) offset: 17h powerup control register configures chip startup speed. this is a special r egister, writing needs to be enabled by writing 10b to reg 3fh first. this register is reset at por and ge ts loaded with the otp fuse contents. bit bit name default access bit description 7 seq_lock 0 r/w 0: additional bits can be fused inside register 16h & 17h 1: otp fusing for register 16h & 17h gets locked, n o more changes can be done. 6:2 fast_start <4:0> 0 0000 r/w 0h: ~900ms start-up time 0eh: ~600ms startup time 1 lin_agc_off 0 r/w 0: line input agc enabled 1: line input agc switched off 0 mic_agc_off 0 r/w 0:microphone input agc enabled 1: microphone input agc switched off table 31. anc_l register name base default anc_l 2-wire serial 80h (otp) offset: 30h left otp microphone input register configures the gain for the left microphone input. this is a special register, writing needs to be ena bled by writing 10b to reg 3fh first. this register is rese t at por and gets loaded with the otp fuse contents . bit bit name default access bit description 7 test_bit_1 1 r for testing purpose only 6:0 micl_vol_otp <6:0> 000 0000 r/w volume settings for left microphone inpu t, adjustable in 127 steps of 0.375db 00 0000: mute 00 0001: 11.25db gain 00 0010: 10.875 db gain .. 11 1110: 35.625db gain 11 1111: 36 db gain
www.austriamicrosystems.com revision 0.90 39 61 as3421 as3422 datasheet r e g i s t e r d e s c r i p t i o n table 32. anc_r register name base default anc_r 2-wire serial 80h (otp) offset: 31h right otp microphone input register configures the gain for the left microphone input. this is a special register, writing needs to be ena bled by writing 10b to reg 3fh first. this register is rese t at por and gets loaded with the otp fuse contents . bit bit name default access bit description 7 test_bit_2 1 r for testing purpose only 6:0 micr_vol_otp <6:0> 000 0000 r/w volume settings for right microphone inp ut, adjustable in 127 steps of 0.375db 00 0000: mute 00 0001: 11.25db gain 00 0010: 10.875 db gain .. 11 1110: 35.625db gain 11 1111: 36 db gain
www.austriamicrosystems.com revision 0.90 40 61 as3421 as3422 datasheet r e g i s t e r d e s c r i p t i o n table 33. mic_mon register name base default mic_mon 2-wire serial 00h (otp) offset: 32h opt microphone monitor mode register configures the gain for the microphone input in mon itor mode. this is a special register, writing needs to be enabled by writing 10b to reg 3fh first. this re gister is reset at por and gets loaded with the otp fuse contents. bit bit name default access bit description 7 mon_mode 0 r/w 0: monitor mode is working with fixed microphone ga in 1: monitor mode uses adjustable gain via the vol pi n 6:0 mic_mon_otp <6:0> 000 0000 r/w volume settings for microphone input dur ing monitor mode, adjustable in 127 steps of 0.375db. if mon_mode bit is set to 1 t he gain can be further adjusted via the vol pin. 00 0000: mute 00 0001: 11.25db gain 00 0010: 10.875 db gain .. 11 1110: 35.625db gain 11 1111: 36 db gain table 34. audio_set register name base default audio_set 2-wire serial 00h (otp) offset: 33h opt audio setting register configures the audio settings. this is a special reg ister, writing needs to be enabled by writing 10b t o reg 3fh first. this register is reset at por and gets l oaded with the otp fuse contents. bit bit name default access bit description 7 no_pb_mode 0 r/w this bit defines if the low power mu sic playback mode is enabled or not. in case the bit is set to 0, music playback mode can be entered by pulling the anc_csda pin low. in case the bit is set to 1 the music playback mode is disabled. pulling the anc_csda pin low has no influ ence. 0: music playback mode enabled 1: music playback mode disabled 6 vol_button_mode 0 r/w if bit is set to 1 the anc_cs da pin allows the user to control the line input gain via pushbuttons. if bit is set to 0, the vo lume control is disabled. please mind that if vol_button_mode bit is set to 1 entering music playback mode via anc_csda pin is not possible any more. 0: volume mode via push-button disabled 1: volume mode via pushbutton enabled 5 line_gain_+3db_otp 0 r/w selects the line input opera ting gain range. if this bit is set the gain range of the line input amplifiers is shifted by +3db. 0: line input gain range from -46.5db...0db 1: line input gain range from 43.5db...+3db 4 mic_mode_otp 0 r/w 0: microphone input stage operating in single ended mode 1: normal operating in mono balanced
www.austriamicrosystems.com revision 0.90 41 61 as3421 as3422 datasheet r e g i s t e r d e s c r i p t i o n 3 hp_mode_otp 0 r/w 0: headphone stage operating in single ended mode 1: normal operating in mono balanced 2:0 lin_mon_atten <6:0> 000 r/w volume settings for line input during monitor mode, adjustable in 7 steps of 6db and mute. 000: 0db gain 001: 6db gain .. 110: 36db gain 111: mute table 34. audio_set register name base default audio_set 2-wire serial 00h (otp) offset: 33h opt audio setting register configures the audio settings. this is a special reg ister, writing needs to be enabled by writing 10b t o reg 3fh first. this register is reset at por and gets l oaded with the otp fuse contents. bit bit name default access bit description
www.austriamicrosystems.com revision 0.90 42 61 as3421 as3422 datasheet r e g i s t e r d e s c r i p t i o n table 35. gp_op register name base default gp_op 2-wire serial 00h (otp) offset: 34h otp general purpose operational amplifier register enables the opamp stages, defines opamp 2 mode and gain and sets the hp input multiplexer. this is a special register, writing needs to be enabled by w riting 10b to reg 3fh first. this register is reset at por and gets loaded with the otp fuse contents. bit bit name default access bit description 7:6 hp_mux_otp<1:0> 00 r/w multiplexes the analog audio signal to hp amp 00: mic: selects qmicl/r output 01:op1: selects qop1l/r outputs 10:op2: selects qop2l/r output 11: open: no signal mixed together with the line in put signal 5:2 op2_otp<3:0> 0000 r/w mode and volume settings for op2, adjustable in 15 steps of 0.75db 0000: op2l in inverting mode 0001: 0 db gain, op2l in non inverting mode 0001: 0.75 db gain, non inverting .., 1110: 9.75db gain, non inverting 1111:.10.5 db gain, non inverting 1 op2_on 0 r/w 0: op2 is switched off 1: left op2 is enabled 0 opl_on 0 r/w 0: op1 is switched off 1: op1 is enabled table 36. otp_sys register name base default otp_sys 2-wire serial 40h (otp) offset: 35h otp system settings register defines several system settings for otp operation. this is a special register, writing needs to be enab led by writing 10b to reg 3fh first. this register is r eset at por and gets loaded with the otp fuse conte nts. bit bit name default access bit description 7 main_lock 0 r/w 0: additional bits can be fused inside the otp 1: otp fusing gets locked, no more changes can be d one 6 test_bit_3 1 r for testing purpose only 5:4 mon_hp_mux <1:0> 00 r/w multiplexes the analog audio signal to hp amp in monitor mode 00: mic: selects qmicl/r output 01: op1: selects qop1l/r outputs 10:op2: selects qop2l/r output 11: open: no signal mixed together with the line in put signal 2 cp_mode_otp 0 r/w this bit controls the operating mod e of the microphone supply charge pump. 0: standard low noise operation 1: increased output voltage 1 mics_cp_off 0 r/w 0: mics charge pump is enabled 1: mics charge pump is switched off 0 i2c 0 r/w 0: i2c and stand alone mode start-up possible 1: chip startsup in i2c mode only
www.austriamicrosystems.com revision 0.90 43 61 as3421 as3422 datasheet r e g i s t e r d e s c r i p t i o n table 37. config_1 register name base default config_1 2-wire serial 00h offset: 3eh otp configuration register controls the clock configuration. this is a special register, writing needs to be enabled by writing 9h to reg 20h first. this register is reset at por and ge ts loaded with the otp fuse contents. bit bit name default access bit description 7:4 0000 n/a 3 extburnclk 0 n/a 0: ext. clock for otp burning disabled 1: ext. clock for otp burning enabled 2:0 000 n/a table 38. config_2 register name base default config_2 2-wire serial 00h offset: 3fh otp access configuration register controls the otp access. this is a special register, writing needs to be enabled by writing 9h to reg 2 0h first. this register is reset at por and gets loade d with the otp fuse contents. bit bit name default access bit description 7:6 000 n/a 5 tm34 0 n/a this register defines the register bank se lection for register tm_reg3435 and tmreg3033. depending on tm34 you c an select either between register bank 14h17h and 10h13h en abled or 30h33h and 34h37h enabled. 0: test mode registers 14h-17h and 10h-13h disabled test mode registers 30h-33h and 34h-37h enabled 1: test mode registers 14h17h and 10h13h enabled test mode registers 30h33h and 34h37h disable d 4 burnsw 0 n/a 0: burn switch from linl to vneg is disabled 1: burn switch from linl to vneg is enabled 3 tm_reg3435 0 n/a 0: test mode for register 34h-35h disabled test mode for register 14h-17h disabled 1: test mode for register 34h35h enabled test mode for register 14h17h enabled 2 tm_reg3033 0 n/a 0: test mode for register 30h-33h disabled test mode for register 10h-13h disabled 1: test mode for register 30h33h enabled test mode for register 10h13h enabled 1:0 otp_mode<1:0> 00 r/w controls the otp access 00: read 01: load 10: write 11: burn
www.austriamicrosystems.com revision 0.90 44 61 as3421 as3422 datasheet a p p l i c a t i o n i n f o r m a t i o n 11 application information 11.1 as3422 feedback application examples figure 35. as3422 feedback application example wit h bluetooth i2c control
www.austriamicrosystems.com revision 0.90 45 61 as3421 as3422 datasheet a p p l i c a t i o n i n f o r m a t i o n figure 36. as3422 feedback application example wit h bluetooth rom version (no i2c control)
www.austriamicrosystems.com revision 0.90 46 61 as3421 as3422 datasheet a p p l i c a t i o n i n f o r m a t i o n figure 37. as3422 schematic - stereo bluetooth fee dback application with i2c control 1 1 2 2 3 3 4 4 d d c c b b a a gnd agnd c3 1u vanc gnd agnd c6 100n c5 10u gnd c13 10uf t-a1 mics gnd c2 10u gnd c1 100n vneg vneg r3 10k r4 10k agnd rc filter networks c10 220nf c9 220nf c8 220nf c7 220nf r5 2k2 c14 4.7uf c12 4.7uf r6 2k2 mics agnd agnd mics speaker right speaker left right anc microphone left anc microphone to be developed individually for each headset. rc filter networks to be developed individually for each headset. qlinl 2 qmicl 3 agnd 4 linl_n 5 linl_p 6 linr_n 8 linr_p 7 csda 9 micl 11 cscl 10 mics 12 micr 13 qmicr 14 qlinr 15 iop1r 16 qop1r 17 iop2r 18 qop2r 19 vss 20 hpl 21 hpvss 22 hpr 23 hpvdd 24 cpp 26 gnd 27 cpn 28 vneg 29 qop2l 30 iop2l 31 qop1l 32 iop1l 1 vbat 25 as3422 vneg 33 u1 as3422 vneg vanc should be a low noise supply in 1 pok 2 en 3 gnd 4 set 5 out 6 in pok en gnd set out u2 as1363-ad gnd r8 47k r7 15k c15 1uf gnd gnd anc power vdcdc vanc caution: exposed pad must be connect to vneg or left unconn ected. exposed pad must not be conne cted to gnd or agnd!
www.austriamicrosystems.com revision 0.90 47 61 as3421 as3422 datasheet a p p l i c a t i o n i n f o r m a t i o n figure 38. as3422 schematic - stereo bluetooth fee dback application with rom version (no i2c control) 1 1 2 2 3 3 4 4 d d c c b b a a gnd agnd c3 1u vanc gnd agnd c6 100n c5 10u gnd c13 10uf t-a1 mics gnd c2 10u gnd c1 100n vneg vneg r3 10k r4 10k agnd rc filter networks c10 220nf c9 220nf c8 220nf c7 220nf r5 2k2 c14 4.7uf c12 4.7uf r6 2k2 mics agnd agnd mics speaker right speaker left right anc microphone left anc microphone to be developed individually for each headset. rc filter networks to be developed individually for each headset. qlinl 2 qmicl 3 agnd 4 linl_n 5 linl_p 6 linr_n 8 linr_p 7 csda 9 micl 11 cscl 10 mics 12 micr 13 qmicr 14 qlinr 15 iop1r 16 qop1r 17 iop2r 18 qop2r 19 vss 20 hpl 21 hpvss 22 hpr 23 hpvdd 24 cpp 26 gnd 27 cpn 28 vneg 29 qop2l 30 iop2l 31 qop1l 32 iop1l 1 vbat 25 as3422 vneg 33 u1 as3422 vneg vanc should be a low noise supply in 1 pok 2 en 3 gnd 4 set 5 out 6 i n i i p ok en gnd set out u2 as1363-ad gnd r8 47k r7 15k c15 1uf gnd gnd anc power vdcdc vanc vanc 1 2 s1 anc on/off gnd 1 t1 testpoint cscl 1 t2 testpoint cscl 1 t3 testpoint vneg caution: exposed pad must be connect to vneg or left unconn ected. exposed pad must not be connec ted to gnd or agnd!
www.austriamicrosystems.com revision 0.90 48 61 as3421 as3422 datasheet a p p l i c a t i o n i n f o r m a t i o n 11.2 as3421 feed forward application examples figure 39. as3421 feed-forward application example with bluetooth i2c control
www.austriamicrosystems.com revision 0.90 49 61 as3421 as3422 datasheet a p p l i c a t i o n i n f o r m a t i o n figure 40. as3421 feed-forward application example with bluetooth rom version (no i2c control)
www.austriamicrosystems.com revision 0.90 50 61 as3421 as3422 datasheet a p p l i c a t i o n i n f o r m a t i o n figure 41. as3421 schematic - stereo feed-forward bluetooth application with i2c control 1 1 2 2 3 3 4 4 d d c c b b a a gnd agnd c3 1u vanc gnd agnd c6 100n c5 10u gnd c13 10f t-a1 mics gnd c2 10u gnd c1 100n vneg vneg r3 10k r4 10k agnd rc filter networks c10 220nf c9 220nf c8 220nf c7 220nf r5 2k2 c14 4.7uf c12 4.7uf r6 2k2 mics agnd agnd mics speaker right speaker left right anc microphone left anc microphone to be developed individually for each headset. rc filter networks to be developed individually for each headset. vanc should be a low noise supply in 1 pok 2 en 3 gnd 4 set 5 out 6 in pok en gnd set out u2 as1363-ad gnd r8 47k r7 15k c15 1uf gnd gnd anc power vdcdc vanc as3421 qmicl 1 agnd 2 linl_n 3 linl_p 4 linr_p 5 linr_n 6 anc_csda 7 mode_cscl 8 micl 9 mics 10 micr 11 qmicr 12 iop1r 13 qop1r 14 hpl 15 hpr 16 hpvdd 17 vbat 18 cpp 19 gnd 20 cpn 21 vneg 22 qop1l 23 iop1l 24 ex_pad 25 u1 as3421 caution: exposed pad must be connect to vneg or left unconn ected. exposed pad must not be connec ted to gnd or agnd!
www.austriamicrosystems.com revision 0.90 51 61 as3421 as3422 datasheet a p p l i c a t i o n i n f o r m a t i o n figure 42. as3421 schematic - stereo feed-forward bluetooth application rom version (no i2c control) 1 1 2 2 3 3 4 4 d d c c b b a a gnd agnd c3 1u vanc gnd agnd c6 100n c5 10u gnd c13 10f t-a1 mics gnd c2 10u gnd c1 100n vneg vneg r3 10k r4 10k agnd rc filter networks c10 220nf c9 220nf c8 220nf c7 220nf r5 2k2 c14 4.7uf c12 4.7uf r6 2k2 mics agnd agnd mics speaker right speaker left right anc microphone left anc microphone to be developed individually for each headset. rc filter networks to be developed individually for each headset. vanc should be a low noise supply in 1 pok 2 en 3 gnd 4 set 5 out 6 i n i i p ok en gnd set out u2 as1363-ad gnd r8 47k r7 15k c15 1uf gnd gnd anc power vdcdc vanc 1 2 s1 anc on/off gnd vanc 1 t1 testpoint cscl 1 t2 testpoint cscl 1 t3 testpoint vneg as3421 qmicl 1 agnd 2 linl_n 3 linl_p 4 linr_p 5 linr_n 6 anc_csda 7 mode_cscl 8 micl 9 mics 10 micr 11 qmicr 12 iop1r 13 qop1r 14 hpl 15 hpr 16 hpvdd 17 vbat 18 cpp 19 gnd 20 cpn 21 vneg 22 qop1l 23 iop1l 24 ex_pad 25 u1 as3421 caution: exposed pad must be connect to vneg or left unconn ected. exposed pad must not be connec ted to gnd or agnd!
www.austriamicrosystems.com revision 0.90 52 61 as3421 as3422 datasheet a p p l i c a t i o n i n f o r m a t i o n 11.3 layout recommendation whereever you have audio circuits mixed with power management layout of the blocks is a critical issue . the as3421/22 has an integrated charge pump which operates at a frequency of 1mhz. if the layout of the pcb is not done properly the c harge pump can directly influence the audio performance of the device. therefore it is ve ry important to make sure that the layout of the ch arge pump is done properly. the layout recommendation shown in figure 43 below shows an example placement of the components of the charge pump. the reference designators of the components used in the example r efer to the schematic shown in figure 37 . it can be seen clearly that the ground pins of al l capacitors as well as the ground pin of as3422 are placed closely. this compact placement of the compo nents help to minimize high frequency cross over currents all over the pcb and therefore helps to improve the audio quality. a dedicated gro und plane on the top (red) layer minimizes the resistance between the ground pads of the compo nents. the ground plane (gnd) is then connected to the analog ground (agnd) at a single point which is indicated with three vias in the exa mple. figure 43. as3422 cp layout recommendation if the physical alignment of the components allows it, it is also recommended to connect the charge pu mp ground plane on top layer directly to the battery ground terminal of your device. the ana logue (agnd) and charge pump ground plane (gnd) ar e then connected together directly at the battery terminal. this concept is also know as star shaped ground concept shown in figure 44 below. figure 44. as3422 star shaped ground concept ia connection to analog round plane (agnd) for component references please refer to figure 24. charge pump ground (gnd) and analog ground (agnd) are directly connected together at negative battery terminal. for component references please refer to figure 24.
www.austriamicrosystems.com revision 0.90 53 61 as3421 as3422 datasheet a p p l i c a t i o n i n f o r m a t i o n the layout examples showed in the examples before are based on as3422. the as3421 has of course a sma ller package than as3422, therefore the alignment of the charge pump componen ts is different. a layout recommendation for as3421 is shown in figure 45 below. figure 45. as3421 cp layout recommendation 11.4 bill of materials the following section shows the bill of materials w hich is necessary to operate the device. the necess ary rc filter networks which are necessary for gain and phase compensation are excl uded. these components very much depend on the acou stic design of each headset. both devices basically need 17 external component for st andard operation without the necessary filter compo nents. the reference designator of the components shown in table 39 refer to the schematics shown in figure 37 and figure 41 . table 39. as3421/22 bill of materials pos reference value/name description count 1 u1 as3421 stereo bluetooth anc headphone driver circ uit 1 2 u2 as1363ad low drop voltage regulator 1 3 c3, c15 1f charge pump flying capacitor; +/ 10% to lerance and ldo support 2 4 c1, c6 100nf pmu blocking capacitors; +/ 10% tolera nce 2 5 c7, c8, c9, c10 220nf audio dc coupling capacitors; +/ 10% tolerance 4 6 c13 10f microphone supply filter capacitor; +/ 10% tolerance 1 7 c12, c14 4.7uf microphone dc coupling capacitors; +/ 5% tolerance 2 8 r5, r6 2k2 microphone bias resistors; +/ 5%toleranc e 2 9 c2, c5 10f pmu blocking capacitors; +/ 10% toleran ce 2 10 r7 15k voltage regulator feedback resistor 1 11 r8 47k voltage regulator feedback resistor 1 12 r3, r4 10k two wire interface pull up resistors; +/ 10% tolerance 2 sum 21 via connection to analog round plane (agnd) for component references please refer to figure 26.
www.austriamicrosystems.com revision 0.90 54 61 as3421 as3422 datasheet a p p l i c a t i o n i n f o r m a t i o n 11.5 pcb footprint recommendation figure 46. as3421 pcb footprint recommendation recommended land pattern pin 1 pin 1 pin 1 caution: please mind that the recommendations are designed according to ipc-7351b standard. the footprints migh t need little changes in order to achieve best reliabili ty in production! top view silk screen silk screen silk screen ow component density recommended land pattern top view medium component density recommended land pattern top view high component density
www.austriamicrosystems.com revision 0.90 55 61 as3421 as3422 datasheet a p p l i c a t i o n i n f o r m a t i o n figure 47. as3422 pcb footprint recommendation recommended land pattern pin 1 pin 1 pin 1 caution: please mind that the recommendations are designed according to ipc-7351b standard. the footprints migh t need little changes in order to achieve best reliabili ty in production! top view silk screen silk screen silk screen ow component density recommended land pattern top view medium component density recommended land pattern top view high component density
www.austriamicrosystems.com revision 0.90 56 61 as3421 as3422 datasheet p a c k a g e d r a w i n g s a n d m a r k i n g 12 package drawings and marking figure 48. qfn marking table 40. package code yywwizz yy ww x zz last two digits of the year manufacturing week plant identifier free choice / traceability code
www.austriamicrosystems.com revision 0.90 57 61 as3421 as3422 datasheet p a c k a g e d r a w i n g s a n d m a r k i n g figure 49. as3421, 24-pin qfn 0.5mm pitch
www.austriamicrosystems.com revision 0.90 58 61 as3421 as3422 datasheet p a c k a g e d r a w i n g s a n d m a r k i n g figure 50. as2322 32-pin qfn 0.5mm pitch
www.austriamicrosystems.com revision 0.90 59 61 as3421 as3422 datasheet r e v i s i o n h i s t o r y revision history note: typos may not be explicitly mentioned under revisio n history. revision date owner description 0.2 25.1.2012 hgt initial release 0.3 14.3.2012 hgt updated low power playback mode and pin description s 0.4 11.6.2012 hgt updated microphone parameters
www.austriamicrosystems.com revision 0.90 60 61 as3421 as3422 datasheet o r d e r i n g i n f o r m a t i o n 13 ordering information the devices are available as the standard products shown in table 41 . note: all products are rohs compliant and austriamicrosys tems green. buy our products or get free samples online at icdi rect: http://www.austriamicrosystems.com/icdirect for further information and requests, please contac t us mailto:sales@austriamicrosystems.com or find your local distributor at http://www.austriamicrosystems.com/distributor table 41. ordering information ordering code description delivery form package as3421eqfp low power ambient noisecancelling speak er driver tape & reel dry pack qfn 24 [4.0x4.0x0.85mm] 0.5mm pitch as3421eqfp500 low power ambient noisecancelling s peaker driver tape & reel dry pack qfn 24 [4.0x4.0x0.85mm] 0.5mm pitch as3422eqfp low power ambient noisecancelling speak er driver tape & reel dry pack qfn 32 [5.0x5.0x0.85mm] 0.5mm pitch as3422eqfp500 low power ambient noisecancelling s peaker driver tape & reel dry pack qfn 32 [5.0x5.0x0.85mm] 0.5mm pitch
www.austriamicrosystems.com revision 0.90 61 61 as3421 as3422 datasheet c o p y r i g h t s copyrights copyright ? 19972012, austriamicrosystems ag, tobe lbaderstrasse 30, 8141 unterpremstaetten, austriae urope. trademarks registered ?. all rights reserved. the material herein may not be reproduced, adapted, merged, translated, stored, o r used without the prior written consent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective compa nies. disclaimer devices sold by austriamicrosystems ag are covered by the warranty and patent indemnification provisio ns appearing in its term of sale. austriamicrosystems ag makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent in fringement. austriamicrosystems ag reserves the rig ht to change specifications and prices at any time and without notice. therefore, prior to de signing this product into a system, it is necessary to check with austriamicrosystems ag for current information. this product is intended for u se in normal commercial applications. applications requiring extended temperature range, unusual environmental requirements, or high reliabi lity applications, such as military, medical lifes upport or lifesustaining equipment are specifically not recommended without additional pro cessing by austriamicrosystems ag for each applicat ion. for shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flo w or test location. the information furnished here by austriamicrosyste ms ag is believed to be correct and accurate. howev er, austriamicrosystems ag shall not be liable to recipient or any third party for any d amages, including but not limited to personal injur y, property damage, loss of profits, loss of use, interruption of business or indirect, special, inci dental or consequential damages, of any kind, in co nnection with or arising out of the furnishing, performance or use of the technical data herein. no obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems ag rendering of technical or oth er services. contact information headquarters austriamicrosystems ag tobelbaderstrasse 30 a8141 unterpremstaetten, austria tel: +43 (0) 3136 500 0 fax: +43 (0) 3136 525 01 for sales offices, distributors and representatives , please visit: http://www.austriamicrosystems.com/contact

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